Bottom-up process

1. Self-assembly

We investigated the effect of increasing the number of polyelectrolyte and gold nanoparticle layers on memory performance, including the size of the memory window (the critical voltage difference between the ‘programmed’ and ‘erased’ states of the devices) and programming speed. We observed a maximum memory window of about 1.8 V, with a stored electron density of 4.2 x 1012 cm-2 in the gold nanoparticle layers, when the devices consist of three polyelectrolyte/gold nanoparticle layers. The reported approach offers new opportunities to prepare nanostructured polyelectrolyte/gold nanoparticle-based memory devices with tailored performance.

2. Anodized aluminum oxide (AAO)

Nanoscale resistive switching memory cells with controlled cell sizes in the range of 25 to 90 nm were successfully fabricated using anodized aluminum oxide templates, and their electrical properties were directly measured using a conductive atomic force microscope. The size of the memory cells was systematically controlled by controlling the pore size of the nanoscale masks. The devices exhibited controllable and reliable resistive switching characteristics suitable for programmable memory applications. The reported approach provides new opportunities for the preparation of nanostructured nonvolatile memory devices with continued device scaling.

3. Electrochemical deposition (ECD)

We report a feasible and versatile way to fabricate high-density, nanoscale memory devices by direct bottom-up filling of memory elements. An ordered array of metal/oxide/metal (copper/copper oxide/copper) nanodots was synthesized with a uniform size and thickness defined by self-organized nanotemplate mask by sequential electrochemical deposition (ECD) of each layer. The fabricated memory devices showed bipolar resistive switching behaviors confirmed by conductive atomic force microscopy. This study demonstrates that ECD with bottom-up growth has great potential to fabricate high-density nanoelectronic devices beyond the scaling limit of top-down device fabrication processes.